Information for "Verilog"
Basic information
| Display title | Verilog |
| Redirects to | Category:Verilog (info) |
| Default sort key | Verilog |
| Page length (in bytes) | 31 |
| Namespace ID | 0 |
| Page ID | 10121 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | rosettacode>AndiPersti |
| Date of page creation | 21:13, 22 April 2014 |
| Latest editor | rosettacode>AndiPersti |
| Date of latest edit | 21:13, 22 April 2014 |
| Total number of edits | 1 |
| Recent number of edits (within past 180 days) | 0 |
| Recent number of distinct authors | 0 |