NRZM: Revision history

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11 March 2024

24 October 2023

  • curprev 15:5215:52, 24 October 2023‎ imported>Bmoore9999‎ 1,127 bytes +114‎ No edit summary
  • curprev 15:5215:52, 24 October 2023‎ imported>Bmoore9999‎ 1,013 bytes +1,013‎ Created page with "=={{header|VHDL}}== ===Encoder=== <syntaxhighlight lang="vhdl"> entity nrzi_encoder is port( clk :in std_logic; d :in std_logic; q :out std_logic ); end entity; architecture rtl of nrzi_encoder is begin process(clk) begin if (d = '1') then if (qint = '0') then qint <= '1'; else qint <= '0'; end if; end if; end process; q <= qint; end architecture;..."
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