Revision as of 04:02, 16 September 2022 (view source) Rdm (talk \| contribs) m (→‎big O) ← Older edit		Revision as of 04:03, 16 September 2022 (view source) Rdm (talk \| contribs) m (→‎big O) Newer edit →
Line 15: In the context of cache management and a relatively modern cpu design, the likelihood of a cache miss and the cost of a cache miss depends on the size of the data set. ~~Looking at~~For estimates on a spec sheet for a relatively modern cpu architecture ([https://www.7-cpu.com/cpu/Haswell.html 2014-ish intel]), this looks like:<pre> Size Latency Increase Description 32 K 4

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