NRZS

VHDL

entity nrzi_encoder is
port(
    clk :in  std_logic;
    d   :in  std_logic;
    q   :out std_logic
);
end entity;

architecture rtl of nrzi_encoder is
begin
    process(clk)   
    begin
        if (d = '1') then
            if (qint = '0') then
                qint <= '1';
            else 
                qint <= '0';
            end if;
        end if;
    end process;
    q <= qint;
end architecture;


entity nrzi_decoder is
port(
    clk :in  std_logic;
    d   :in  std_logic;
    q   :out std_logic
);
end entity;

architecture rtl of nrzi_decoder is
    signal lastd :std_logic := '0';
begin

    process(clk)
    begin
        if (rising_edge(clk)) then
            if (d = lastd) then
                q <= '0';
            else 
                q <= '1';
            end if;
            lastd <= d;
        end if;
    end process;

end architecture;