NRZS: Difference between revisions
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|'''NRZ(S)''' |
|'''NRZ(S)''' |
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=={{header|FreeBASIC}}== |
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FreeBASIC does not have native support for some of the features used in the VHDL examples, so these codes are a simplification. |
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In both cases, data() is the input array that contains the data to be encoded or decoded, and signal() is the output array that will contain the encoded signal or the decoded data. Both arrays must have the same length. The encoded signal and data are represented as arrays of integers, where '0' represents a low level and '1' represents a high level. |
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====Encoder==== |
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<syntaxhighlight lang="vbnet">Sub NRZS_Encoder (dato() As Integer, signal() As Integer) |
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Dim As Integer i, level = 0 |
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For i = Lbound(dato) To Ubound(dato) |
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If dato(i) = 0 Then level = Not level |
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signal(i) = level |
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Next i |
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====Decoder==== |
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<syntaxhighlight lang="vbnet">Sub NRZS_Decoder (signal() As Integer, dato() As Integer) |
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Dim As Integer i, lastLevel = signal(Lbound(signal)) |
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For i = Lbound(signal) + 1 To Ubound(signal) |
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If signal(i) = lastLevel Then |
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lastLevel = signal(i) |
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Next i |
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End Sub</syntaxhighlight> |
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===Encoder=== |
===Encoder=== |
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<syntaxhighlight lang="vhdl"> |
<syntaxhighlight lang="vhdl"> |
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library ieee; |
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use ieee.std_logic_1164.all; |
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port( |
port( |
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clk :in std_logic; |
clk :in std_logic; |
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end entity; |
end entity; |
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architecture rtl of |
architecture rtl of nrzs_encoder is |
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function nrzi_s( |
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signal curr :in std_logic; |
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signal prev :in std_logic |
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) return std_logic is |
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if (curr = '0') then |
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else |
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end if; |
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end function; |
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begin |
begin |
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process(clk) |
process(clk) |
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begin |
begin |
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q <= nrzi_s(d, q); |
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end process; |
end process; |
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q <= qint; |
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end architecture; |
end architecture; |
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</syntaxhighlight> |
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===Decoder=== |
===Decoder=== |
Latest revision as of 20:07, 11 March 2024
NRZ(S) | NRZS | Non-return-to-zero space | Serializer mapping {0: toggle, 1: constant}. |
FreeBASIC
FreeBASIC does not have native support for some of the features used in the VHDL examples, so these codes are a simplification.
In both cases, data() is the input array that contains the data to be encoded or decoded, and signal() is the output array that will contain the encoded signal or the decoded data. Both arrays must have the same length. The encoded signal and data are represented as arrays of integers, where '0' represents a low level and '1' represents a high level.
Encoder
Sub NRZS_Encoder (dato() As Integer, signal() As Integer)
Dim As Integer i, level = 0
For i = Lbound(dato) To Ubound(dato)
If dato(i) = 0 Then level = Not level
signal(i) = level
Next i
End Sub
Decoder
Sub NRZS_Decoder (signal() As Integer, dato() As Integer)
Dim As Integer i, lastLevel = signal(Lbound(signal))
For i = Lbound(signal) + 1 To Ubound(signal)
If signal(i) = lastLevel Then
dato(i - 1) = 1
Else
dato(i - 1) = 0
lastLevel = signal(i)
End If
Next i
End Sub
VHDL
Encoder
library ieee;
use ieee.std_logic_1164.all;
entity nrzs_encoder is
port(
clk :in std_logic;
d :in std_logic;
q :out std_logic
);
end entity;
architecture rtl of nrzs_encoder is
function nrzi_s(
signal curr :in std_logic;
signal prev :in std_logic
) return std_logic is
if (curr = '0') then
return not prev;
else
return prev;
end if;
end function;
begin
process(clk)
begin
q <= nrzi_s(d, q);
end process;
end architecture;
Decoder
entity nrzi_decoder is
port(
clk :in std_logic;
d :in std_logic;
q :out std_logic
);
end entity;
architecture rtl of nrzi_decoder is
signal lastd :std_logic := '0';
begin
process(clk)
begin
if (rising_edge(clk)) then
if (d = lastd) then
q <= '0';
else
q <= '1';
end if;
lastd <= d;
end if;
end process;
end architecture;