Logical operations: Difference between revisions
Content added Content deleted
(Logical operations in QBasic and Yabasic) |
(Logical operations en Verilog) |
||
| Line 3,746: | Line 3,746: | ||
} |
} |
||
}</lang> |
}</lang> |
||
=={{header|Verilog}}== |
|||
<lang Verilog>module main; |
|||
integer a, b; |
|||
initial begin |
|||
a = 1; //true |
|||
b = 0; //false |
|||
$display(a && b); //AND |
|||
$display(a || b); //OR |
|||
$display(!a); //NOT |
|||
$finish ; |
|||
end |
|||
endmodule</lang> |
|||
=={{header|Visual Basic .NET}}== |
=={{header|Visual Basic .NET}}== |
||