User:Rdm: Difference between revisions
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(Dumping this here until I can think of a better place for it, possibly on a different site...) |
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1024 M 44 + 57 ns 1 + ns</pre> |
1024 M 44 + 57 ns 1 + ns</pre> |
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Here, a "cycle" is a clock cycle, and depending on type of instructions being used, a cpu core may execute 1 instruction per cycle, 2 instructions per cycle, 4 instructions per cycle or even (in carefully limited contexts) 8 instructions per cycle. (A 3.5GHz clock would have a 0.286ns clock cycle.) |
Here, a "cycle" is a clock cycle, and depending on type of instructions being used, a cpu core may execute 1 instruction per cycle, 2 instructions per cycle, 4 instructions per cycle or even (in carefully limited contexts) 8 instructions per cycle. (A 3.5GHz clock would have a 0.286ns clock cycle.) |
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In other words, when working with a gigabyte of memory on that machine, a single instruction with a cache miss might cost the time of almost 1100 instructions to (in extreme cases) almost 8800 instructions. |
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Of course the above simplifications focused purely on a single cpu architecture, and ignoring memory architecture. |
Of course the above simplifications focused purely on a single cpu architecture, and ignoring memory architecture. |
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