Rdm

Joined 24 August 2022
A note on Special:RecentChanges
(A note on Special:RecentChanges)
 
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== Recent Changes ==
 
The reports on tasks not implemented in each language no longer function, after the miraheze migration. A crude workaround is to frequently poll the RecentChanges page and look there for task pages which have not been implemented in a language. But the [[Special:RecentChanges]] link from the site nave on the left has also gone missing. You can still find it with an extra hop into [[Special:SpecialPages]].
 
== big O ==
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In the context of cache management and a relatively modern cpu design, the likelihood of a cache miss and the cost of a cache miss depends on the size of the data set.
 
LookingFor atestimates on a spec sheet for a relatively modern cpu architecture ([https://www.7-cpu.com/cpu/Haswell.html 2014-ish intel]), this looks like:<pre> Size Latency Increase Description
 
32 K 4
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In other words, when working with a gigabyte of memory on that machine, a single instruction with a cache miss might cost the time of almost 1100 instructions to (in extreme cases) almost 8800 instructions.
 
Of course, the above simplifications focused purely on a single cpu architecture, and ignoringignored variations in memory architecture.
 
And there are other issues -- for example, when two different cores are accessing the same memory, that tends to introduce cache management conflicts which slow things down.
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