Talk:Four bit adder: Difference between revisions
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I think the "processor" can have as instruction set BF, with the understanding that <tt>.</tt> and <tt>,</tt> can interface the cpu to any suitable device (that must be projected purposely) and likely more instructions for jump could be useful to augment performance (the <nowiki>[</nowiki> needs look-ahead and a <nowiki>[</nowiki>-stack ...). Currently my ideas about how all this can be realized are rather foggy; however I've installed some VHDL tools, going to see how this task would look with it. -[[User:ShinTakezou|ShinTakezou]] 10:36, 17 June 2010 (UTC)
:For a latch, two nor gates with their outputs cross-wired to the other's input should be sufficient? You do need to represent their "previous state", which complicates things, but I do not think you need additional logic? --[[User:Rdm|Rdm]] 12:20, 17 June 2010 (UTC)
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