Logical operations: Difference between revisions
Logical operations en Verilog
(Logical operations in QBasic and Yabasic) |
(Logical operations en Verilog) |
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}
}</lang>
=={{header|Verilog}}==
<lang Verilog>module main;
integer a, b;
initial begin
a = 1; //true
b = 0; //false
$display(a && b); //AND
$display(a || b); //OR
$display(!a); //NOT
$finish ;
end
endmodule</lang>
=={{header|Visual Basic .NET}}==
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