Four bit adder: Difference between revisions

Content added Content deleted
Line 3,950: Line 3,950:


=={{header|MyHDL}}==
=={{header|MyHDL}}==
To interpret and run this code you will need a copy of Python3, and the MyHDL library from myhdl.org.
To interpret and run this code you will need a copy of Python3, and the MyHDL library from myhdl.org (pip3 install myhdl).


The test code simulates the adder and exports trace wave file for debug support. Verilog and VHDL files are exported for hardware synthesis.
The test code simulates the adder and exports trace wave file for debug support. Verilog and VHDL files are exported for hardware synthesis.