Four bit adder: Difference between revisions
Content added Content deleted
m (centered titles of illustrations better.) |
m (added whitespace around the names of italicized gates.) |
||
Line 5: | Line 5: | ||
This design can be realized using four [[wp:Adder_(electronics)#Full_adder|1-bit full adder]]s. |
This design can be realized using four [[wp:Adder_(electronics)#Full_adder|1-bit full adder]]s. |
||
Each of these 1-bit full adders can be built with two [[wp:Adder_(electronics)#Half_adder|half adder]]s and an ''or'' [[wp:Logic gate|gate]]. |
Each of these 1-bit full adders can be built with two [[wp:Adder_(electronics)#Half_adder|half adder]]s and an ''or'' [[wp:Logic gate|gate]]. ; |
||
⚫ | |||
Finally a half adder can be made using an ''xor'' gate and an ''and'' gate. |
|||
⚫ | |||
⚫ | |||
⚫ | |||
⚫ | |||
⚫ | |||
⚫ | If there is not a ''bit type'' in your language, to be sure that the ''not'' does not "invert" all the other bits of the basic type (e.g. a byte) we are not interested in, you can use an extra ''nand'' (''and'' then ''not'') with the constant '''1''' on one input. |
||
⚫ | |||
{| |
{| |