Category:MIPS Assembly: Difference between revisions
m
rearranged some chapters for better flow
Puppydrum64 (talk | contribs) m (→Registers) |
Puppydrum64 (talk | contribs) m (rearranged some chapters for better flow) |
||
Line 16:
<lang mips>li t0, 0
subiu t0,1</lang>
==Pseudo-instructions==▼
MIPS has a form of "hardware macros" that help out with tasks that it can't do alone. It has a special register that exists solely for the execution of these macros, which is not usable by the programmer directly. Assemblers will generally let you use these "pseudo-instructions" as if they were real instructions, even if they technically don't exist. Knowing what instructions are "real" and which ones aren't usually doesn't matter much, since you won't be doing self-modifying code on the MIPS anyway (for reasons we'll get into later)▼
==Alignment==
Unlike other RISC CPUs, MIPS actually <i>can</i> load data from unaligned memory without faulting. However, it can't use the normal <code>LW</code> and <code>SW</code> commands in order to do so. It should be noted that this only applies to data; instructions do need to be 32-bit aligned at all times. Most assemblers have an <code>.align</code> directive that can do the job easily.
▲==Pseudo-instructions==
▲MIPS has a form of "hardware macros" that help out with tasks that it can't do alone. It has a special register that exists solely for the execution of these macros, which is not usable by the programmer directly. Assemblers will generally let you use these "pseudo-instructions" as if they were real instructions, even if they technically don't exist. Knowing what instructions are "real" and which ones aren't usually doesn't matter much, since you won't be doing self-modifying code on the MIPS anyway (for reasons we'll get into later)
==Bi-Endian==
| |||